Algorithms and Architectures for Low Power Spike Sorting

Front-end integrated circuits for signal processing are useful in neuronal recording systems that engage a large number of electrodes. Detection, alignment, and sorting of the spike data at the frontend reduces the data bandwidth and enables wireless communication. Without such data reduction, large data volumes need to be transferred to a host computer and typically heavy cables are required which constrain the patient or test animal. We explore Neuroprocessor electronic chips for portable applications. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communication to a host computer. It can dissipate only a limited amount of power, due to supply constraints and heat restrictions. We introduce hardware architectures for automatic spike sorting algorithms in Neuroprocessors, designed for low power. Some of the algorithms are based on principal component analysis. Others employ a novel Integral Transform analysis and achieve 98% of the precision of a PCA sorter, while requiring only 2.5% of the computational complexity. The algorithms execute autonomously, but require off-line training and setting of computational parameters. We employ pre-recorded neuronal signals to evaluate the accuracy of the proposed algorithms and architectures: The recorded data are processed by a standard PCA spike sorting software algorithm, as well as by the several hardware algorithms, and the outcomes are compared.